A method is proposed by which in a semiconductor memory such as a DRAM, if row-related and column-related circuit blocks do not operate, supply of a power supply voltage to those circuit blocks is stopped to thereby reduce a leakage current flowing through the inoperative circuit blocks (see, for example, Japanese Patent Application Laid-Open Nos. 2008-27547 and 2010-135047). Another method is proposed by which in a DRAM, an operating frequency is recognized on the basis of a column address strobe (CAS) latency set in a mode register to change a capacity of generating an internal power supply voltage by using a voltage generation unit based on this recognized operating frequency, thereby reducing dissipation power (see, for example, Japanese Patent Application Laid-Open No. 2009-181638). A further method is proposed by which in a pseudo SRAM, when a standby mode in which refresh operations are performed is recovered from a deep standby mode in which the refresh operations are stopped, the operating frequency of the voltage generation unit generating the internal power supply voltage is increased to thereby rapidly set the internal voltage to a desired value (see, for example, Japanese Patent Application Laid-Open No. 2008-117525).
For example, in the case of forming a plurality of voltage generation units corresponding to circuit blocks respectively, the power supply voltage generation capacity of each of the voltage generation units is designed to match the maximum dissipation power of the corresponding circuit blocks. However, the plurality of circuit blocks are not always operating at the maximum dissipation power. If the voltage generation unit has an excessive power supply voltage generation capacity, the semiconductor memory has increased dissipation power.